FIG. 1 is a circuit diagram of a data output control circuit for a semiconductor storage device incorporated herein to disclose the background art of this invention. As seen from FIG. 1, data are inputted to an output circuit section OC via data lines d and d. The data are supplied to NOR gates G1 and G2. In order to access at high speed, it is necessary to equalize the data lines d and d. This equalization is executed by applying a clock pulse .PHI. (ATD pulse) which is outputted when an ATD (address transition detector) detects a change of an address, to the gate of a transistor M3 coupling the data lines d and d. The clock pulse d is also applied to the NOR gates G1 and G2 so as to prevent output from changing. The output nodes N4 and N5 of the NOR gates G1 and G2 are connected to the gates of output transistors M1 and M2, respectively. The output transistors M1 and M2 are connected in series. The output from the transistors M1 and M2 is derived from an output node (interconnection node) N1 thereof. A supply potential Vcc and ground potential Vss are supplied to the output circuit section OC from a d.c. power source E. A capacitor C2 is equivalently connected in parallel with the d.c. power source E. A reactor L2 and resistor R2 are equivalently connected at the supply potential Vcc side of the d.c. power source E, and a reactor L3 and resistor R3 are equivalently connected at the ground potential Vss side. Also in the power supply path of the output circuit section OC, a resistor R4 is equivalently connected at the supply potential Vcc side downstream of an input node N2, and a resistor R5 is equivalently connected at the ground potential Vss side downstream of an input node N3. Also at the output side of the output circuit section OC, there exists a serial circuit of a resistor R1, reactor L1, and capacitor C1.
The data output control circuit constructed as above will be described with reference to the timing chart shown in FIG. 2. FIG. 2(a) represents the state of the supply potential Vcc at the input node N2, FIG. 2(b) represents a change of an address, FIG. 2(c) represents the clock pulse .PHI. , FIG. 2(d) represents the state of the data line d, FIG. 2(e) represents the state of the data line d, FIG. 2(f) represents the state at the output node N4 of the NOR gate G1, FIG. 2(g) represents the state at the output node N5 of the NOR gate G2, FIG. 2(h) represents the state at the output node N1 of the output transistors M1 and M2, and FIG. 2(i) represents the state of the ground potential Vss at the input node N3.
As shown in FIG. 2(b), an address signal changes at time t1 (t6) so that there is obtained a clock pulse .PHI..sub.1 which takes a high level from time t2 to time t3. As seen from FIG. 1, this clock pulse .PHI..sub.1 is inputted to the gate of the transistor M3 to turn it on. Accordingly, the potentials of the data lines d and d take medium values during the period from time t2 to time t3 as shown in FIGS. 2(d) and 2(e). The clock pulse .PHI. is also applied to the NOR gates G1 and G2 so that the potentials at the output nodes N4 and N5 of the NOR gates G1 and G2 take a low level during the period from time t2 to time t3 as shown in FIGS. 2(f) and 2(g). The outputs of the NOR gates G1 and G2 are inputted to the gates of the output transistors M1 and M2. A data having an output waveform as shown in FIG. 1(h) is obtained at the output node N1 of the output transistors M1 and M2. The equalized level by the clock pulse is a medium potential between the supply potential Vcc and ground potential Vss. With this medium potential, the output transistors M1 and M2 do not turn on at the same time. Accordingly, a through-current is controlled not to flow from the supply potential Vcc side to the ground potential Vss side via the output transistors M1 and M2.
In order to control the through-current not to flow through the output transistors M1 and M2 during the 10 equalizing operation, a circuit configuration as shown in FIG. 3 is also known. This circuit forms a latch circuit by NOR gates G1 and G2 to hold the previous data during the equalizing operation. If this circuit is used, the number of gates for data access increases by one stage, thereby disabling high speed access.
A conventional data output control circuit is constructed as described above. Accordingly, when the data is outputted, the capacitor C1 present at the output side load is charged and discharged at high speed. Fluctuation of the supply potential Vcc and ground potential Vss due to this charge/discharge is inevitable. Specifically, as shown in FIG. 1, the capacitor C2 is equivalently connected in parallel with the d.c. power source E. The reactor L2 and resistor R2 are equivalently connected at the supply potential Vcc side of the d.c. power source E, and the reactor L3 and resistor R3 are equivalently connected at the ground potential Vss side. Also in the power supply path of the output circuit section OC, the resistor R4 is equivalently connected at the supply potential Vcc side downstream of the input node N2, and the resistor R5 is equivalently connected at the ground potential Vss side downstream of the input node N3. As a result, if the load side is accessed at high speed, it is inevitable that the levels at the input nodes N2 and N3 of the supply potential Vcc and ground potential Vss will fluctuate. This fluctuation of the potentials Vcc and Vss results in noise within an output signal, which may become a cause of an erroneous operation of the semiconductor circuit. In other words, as shown in FIG. 4, if there is a fluctuation of the supply potential Vcc and ground potential Vss, this operation is equivalent to that noises are relatively introduced within an input signal even if the input signal has actually no noise. For this reason, there is a high possibility of erroneous operations, for example, ATD may operate erroneously to generate the clock pulse .PHI..
In the data output control circuit shown in FIG. 1, if noise are generated on the supply potential Vcc and ground potential Vss during the period from time t4 to time t5 as shown in FIGS. 2(a) and 2(i), ATD may operate erroneously to generate the clock pulse having a high level during the period from time t4 to time t5 as indicated by a broken line in FIG. 2(c). In this case, the output impedances of the output transistors M1 and M2 become high because of the clock pulse .PHI..sub.2 between the period from time t4 to time t5. Accordingly, the potential at the output node N1 rising up after the access will stop its rise during the period from time t4 to time t5 as indicated by a broken line in FIG. 2(h). When the clock pulse .PHI. returns to the L level at time t5, the output high impedance state is released and resumes the access of the output. In other words, after time t5, the potential at the node N1 rises as shown in FIG. 2(h). Namely, there is a delay in access. This is a significant problem for a circuit requiring a high speed access.